HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 153

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access
or 16-bit access for the corresponding areas.
Bits 7 to 0
ABW7 to ABW0
0
1
ABWCR specifies the data bus width of external memory areas. The data bus width of on-chip
memory and registers is fixed, and does not depend on ABWCR settings. These settings are
therefore invalid in the single-chip modes (modes 6 and 7).
6.2.2
ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two
states or three states.
Bit
Initial value
Read/Write
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is accessed in two or three states.
Bits 7 to 0
AST7 to AST0
0
1
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and
registers are accessed in a fixed number of states that does not depend on ASTCR settings. These
settings are therefore meaningless in the single-chip modes (modes 6 and 7).
Access State Control Register (ASTCR)
AST7
R/W
7
1
Description
Areas 7 to 0 are 16-bit access areas
Areas 7 to 0 are 8-bit access areas
Description
Areas 7 to 0 are accessed in two states
Areas 7 to 0 are accessed in three states
AST6
R/W
6
1
Bits selecting number of states for access to each area
AST5
R/W
5
1
AST4
R/W
4
1
Rev. 2.00 Sep 20, 2005 page 113 of 800
AST3
R/W
3
1
AST2
R/W
2
1
Section 6 Bus Controller
AST1
REJ09B0260-0200
R/W
1
1
(Initial value)
AST0
R/W
0
1