HD64F3026X25 Renesas Electronics America, HD64F3026X25 Datasheet - Page 26

• Manufacturer Part Number: HD64F3026X25
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3026X25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Figure 4.7
Section 5 Interrupt Controller
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Figure 5.7
Figure 5.8
Section 6 Bus Controller
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Figure 6.10
Figure 6.11
Figure 6.12
Figure 6.13
Figure 6.14
Rev. 2.00 Sep 20, 2005 page xxiv of xxxviii
Reset Sequence (Modes 2 and 4)......................................................................... 76
Reset Sequence (Mode 6) .................................................................................... 77
Interrupt Sources and Number of Interrupts ........................................................ 78
Stack after Completion of Exception Handling ................................................... 79
Operation when SP Value is Odd ........................................................................ 81
Interrupt Controller Block Diagram..................................................................... 84
Block Diagram of Interrupts IRQ
Timing of Setting of IRQnF................................................................................. 96
Process Up to Interrupt Acceptance when UE = 1............................................... 101
Interrupt Masking State Transitions (Example)................................................... 103
Process Up to Interrupt Acceptance when UE = 0............................................... 104
Interrupt Exception Handling Sequence .............................................................. 105
Contention between Interrupt and Interrupt-Disabling Instruction...................... 107
Block Diagram of Bus Controller........................................................................ 110
Access Area Map for Each Operating Mode ....................................................... 124
Memory Map in 16-Mbyte Mode
(H8/3024F-ZTAT, H8/3024 Mask ROM Verion) (1).......................................... 125
Memory Map in 16-Mbyte Mode
(H8/3026F-ZTAT, H8/3026 Mask ROM Verion) (2).......................................... 126
C S
Sample Address Output in Each Address Update Mode
(Basic Bus Interface, 3-State Space).................................................................... 130
Access Sizes and Data Alignment Control (8-Bit Access Area) ......................... 131
Access Sizes and Data Alignment Control (16-Bit Access Area) ....................... 132
Bus Control Signal Timing for 8-Bit, Three-State-Access Area ......................... 134
Bus Control Signal Timing for 8-Bit, Two-State-Access Area ........................... 135
Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
(Byte Access to Even Address) ........................................................................... 136
Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
(Byte Access to Odd Address)............................................................................. 137
Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
(Word Access) ..................................................................................................... 138
Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
(Byte Access to Even Address) ........................................................................... 139
Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)
(Byte Access to Odd Address)............................................................................. 140
n Signal Output Timing (n = 0 to 7)................................................................ 129
0
to IRQ
5
.......................................................... 95