DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 99

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Memory Blocks in Stratix V Devices
Overview
May 2011 Altera Corporation
Packed Mode Support
Address Clock Enable Support
Stratix V M20K memory blocks support packed mode. The packed mode feature
packs two independent single-port RAMs into one memory block. The Quartus II
software automatically implements packed mode where appropriate by placing the
physical RAM block in true dual-port mode and using the MSB of the address to
distinguish between the two logical RAMs. The size of each independent single-port
RAM must not exceed half of the target block size.
Stratix V embedded memory blocks support address clock enable, which holds the
previous address value for as long as the signal is enabled (addressstall = 1). When
the memory blocks are configured in dual-port mode, each port has its own
independent address clock enable. The default value for the address clock enable
signal is low (disabled).
Figure 2–2
referred to by the port name addressstall.
Figure 2–2. Address Clock Enable
shows an address clock enable block diagram. The address clock enable is
addressstall
address[0]
address[N]
clock
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
1
0
1
0
address[0]
address[N]
register
register
address[0]
address[N]
2–5