DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 37

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Electrical Characteristics
Table 2–10. Pin Capacitance for Stratix V Devices—Preliminary
Table 2–12. Internal Weak Pull-Up Resistor for Stratix V Devices—Preliminary
May 2011 Altera Corporation
C
C
C
R
Notes to
(1) All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins.
(2) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak pull-down resistor is
(3) Pin pull-up resistance values may be lower if an external source drives the pin higher than V
IOTB
IOLR
OUTFB
PU
Symbol
approximately 25 k
Symbol
Table
2–12:
Value of the I/O pin pull-up resistor before
and during configuration, as well as user
mode if you enable the programmable
pull-up resistor option.

Pin Capacitance
Table 2–10
Hot Socketing
Table 2–11
Table 2–11. Hot Socketing Specifications for Stratix V Devices—Preliminary
Internal Weak Pull-Up Resistor
Table 2–12
Input capacitance on the top and bottom I/O pins
Input capacitance on the left and right I/O pins
Input capacitance on dual-purpose clock output and feedback pins
I
I
I
I
Notes to
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |I
(2) These specifications are preliminary.
IOPIN (DC)
IOPIN (AC)
XCVR-TX (DC)
XCVR-RX (DC)
capacitance and dv/dt is the slew rate.
Symbol
Description
Table
(2)
(2)
lists the hot socketing specifications for Stratix V devices.
lists the Stratix V device family pin capacitance.
lists the weak pull-up resistor values for Stratix V devices.
2–11:
DC current per I/O pin
AC current per I/O pin
DC current per transceiver transmitter pin
DC current per transceiver receiver pin
Description
Description
V
CCIO
1.35 ±5%
1.25 ±5%
3.0 ±5%
2.5 ±5%
1.8 ±5%
1.5 ±5%
1.2 ±5%
(V)
Conditions
Stratix V Device Handbook Volume 1: Overview and Datasheet
(3)
CCIO
(Note
.
Min
IOPIN
—
—
—
—
—
—
—
1),
| = C dv/dt, in which C is the I/O pin
(2)
Typical
Typ
25
25
25
25
25
25
25
5.5
5.5
5.5
Maximum
8 mA
100 mA
300 A
50 mA
(1)
Max
—
—
—
—
—
—
—
Unit
pF
pF
pF
Unit
k
k
k
k
k
k
k
2–9