DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 212

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–36
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
1
Non-Voltage-Referenced Standards
Each I/O bank of a Stratix V device has its own VCCIO pins and supports only one
V
support any number of input signals with different I/O standard assignments if it
meets the V
For output signals, a single I/O bank supports non-voltage-referenced output signals
that are driving at the same voltage as V
V
For example, an I/O bank with a 2.5-V V
inputs and outputs as well as 3.0-V LVCMOS inputs (but not 3.0-V LVCMOS output
or bidirectional pins).
Voltage-Referenced Standards
To accommodate voltage-referenced I/O standards, each Stratix V device’s I/O bank
supports multiple VREF pins feeding a common V
VREF pins increases as device density increases. If these pins are not used as VREF pins,
they cannot be used as GPIO pins and must be tied to V
only have a single V
An I/O bank featuring single-ended or differential standards can support
voltage-referenced standards if all voltage-referenced standards use the same V
setting.
For performance reasons, voltage-referenced input standards use their own V
level as the power source. This feature allows you to place voltage-referenced input
signals in an I/O bank with a V
HSTL-15 input pins in an I/O bank with 2.5-V V
voltage-referenced input with R
match the voltage of the input standard. R
HSTL-15 I/O standard when V
Voltage-referenced bidirectional and output signals must be the same as the I/O
bank’s V
bank with a 2.5-V V
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards
An I/O bank can support both voltage-referenced and non-voltage-referenced pins by
applying each of the rule sets individually. For example, an I/O bank can support
SSTL-18 inputs and 1.8-V inputs and outputs with a 1.8-V V
Similarly, an I/O bank can support 1.5-V standards, 1.8-V inputs (but not outputs),
and HSTL and HSTL-15 I/O standards with a 1.5-V V
V
One VCCPD pin is shared in the particular group of I/O banks. For example, the I/O
banks with the same number 7A, 7B, 7C, and 7D form a group that share the same
VCCPD pin. This is true for all I/O banks except for I/O banks 3A, 3B, 3C, 3D, and 3E.
Banks 3A and 3B form a group with one VCCPD pin while banks 3C, 3D, and 3E form a
different group with its own VCCPD pin.
Not all Stratix V device packages have bank 3E.
CCPD
CCIO
CCIO
, either 1.2, 1.25, 1.35, 1.5, 1.8, 2.5, or 3.0 V. An I/O bank can simultaneously
value, it can only drive out that one value for non-voltage-referenced signals.
Restriction
CCIO
CCIO
voltage. For example, you can only place SSTL-2 output pins in an I/O
and V
CCIO
CCIO
CCPD
.
voltage level and a single V
requirement (refer to
CCIO
CCIO
T
OCT enabled requires the V
is 2.5 V.
of 2.5 V or below. For example, you can place
CCIO
CCIO
T
OCT cannot be supported for the
. Because an I/O bank can only have one
setting can support 2.5-V standard
CCIO
REF
Table 5–2 on page
REF
Chapter 5: I/O Features in Stratix V Devices
bus. The number of available
. However, the
CCIO
CCIO
voltage level at a given time.
and 0.75-V V
CCIO
or GND. Each bank can
CCIO
May 2011 Altera Corporation
and a 0.9-V V
of the I/O bank to
5–3).
Design Considerations
REF
.
CCPD
REF
REF
.