DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 250

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

7–6
Table 7–2. Number of DQ/DQS Groups in Stratix V Devices per Side
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
5SGXB5
5SGXB6
5SGSD2
5SGSD3
5SGSD3
5SGSD4
5SGSD5
5SGSD6
5SGSD8
5SGTC5
5SGTC7
5SEE9
5SEEB
Notes to
(1) These numbers are preliminary until the devices are available.
(2) Some of the x4 groups are using RZQ pins. If you use the Stratix V calibrated OCT feature, you cannot use these groups.
(3) The number is still not available.
Device
Table
7–2:
1517-pin FineLine BGA
1760-pin FineLine BGA
484-pin FineLine BGA
780-pin FineLine BGA
1152-pin FineLine BGA
1152-pin FineLine BGA
1517-pin FineLine BGA
1517-pin FineLine BGA
1932-pin FineLine BGA
1517-pin FineLine BGA
1517-pin FineLine BGA
1932-pin FineLine BGA
Package
Left/Right
Bottom
Top
Left/Right
Bottom
Top
Left/Right
Bottom
Top
Left/Right
Bottom
Top
Left/Right
Bottom
Top
Left/Right
Bottom
Top
Left/Right
Bottom
Top
Left/Right
Bottom
Top
Left/Right
Bottom
Top
Left/Right
Bottom
Top
Left/Right
Bottom
Top
Left/Right
Bottom
Top
Side
(Note
x4
36
36
50
50
50
42
58
58
46
40
62
66
50
50
58
58
70
70
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
Chapter 7: External Memory Interfaces in Stratix V Devices
0
0
0
0
0
0
0
0
0
(2)
1)—Preliminary (Part 2 of 2)
x8/x9
18
18
25
25
25
21
29
29
23
20
31
33
25
25
29
29
35
35
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
0
0
0
0
0
0
0
0
0
x16/x18
May 2011 Altera Corporation
Memory Interface Pin Support
11
11
12
10
14
14
10
10
15
16
12
12
14
14
16
16
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
0
8
8
0
0
0
0
0
0
0
0
x32/x36
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
0
3
3
0
4
4
0
4
3
0
6
6
0
3
4
0
6
6
0
4
5
0
6
6
0
6
6