DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 215

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
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SV51007-1.2
Overview
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
May 2011
May 2011
SV51007-1.2
This chapter describes the significant advantages of the high-speed differential I/O
interfaces and the dynamic phase aligner (DPA) over single-ended I/Os and their
contribution to the overall system bandwidth achievable with Stratix
The following sections describe the Stratix V high-speed differential I/O interfaces
and DPA in detail:
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All Stratix V devices have built-in serializer/deserializer (SERDES) circuitry that
supports high-speed LVDS interfaces at data rates of up to 1.434 Gbps. SERDES
circuitry is configurable to support source-synchronous communication protocols
such as RapidIO™, XSBI, serial peripheral interface (SPI), and asynchronous protocols
such as SGMII and Gigabit Ethernet (GbE).
The Stratix V device family has the following dedicated circuitry for high-speed
differential I/O support:
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“Locations of the I/O Banks” on page 6–3
“LVDS Channels” on page 6–3
“LVDS SERDES” on page 6–6
“Differential Transmitter” on page 6–7
“Differential Receiver” on page 6–11
“LVDS Interface with the Use External PLL Option Enabled” on page 6–21
“Fractional PLLs and Stratix V Clocking” on page 6–22
“Source-Synchronous Timing Budget” on page 6–22
“Differential Pin Placement Guidelines” on page 6–29
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment
DPA
Synchronizer (FIFO buffer)
Phase-locked loops (PLLs)
6. High-Speed Differential I/O Interfaces
and DPA in Stratix V Devices
®
V FPGAs.
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