DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 186

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–10
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
3.3-V I/O Interface
External Memory Interfaces
High-Speed Differential I/O with DPA Support
Stratix V I/O buffers support 3.3-V I/O standards. You can use them as transmitters
or receivers in your system. The output high voltage (V
input high voltage (V
standards specifications defined by EIA/JEDEC Standard JESD8-B with margin when
the Stratix V V
To ensure device reliability and proper operation when interfacing with a 3.3-V I/O
system using Stratix V devices, do not violate the absolute maximum ratings of the
devices. Altera recommends performing IBIS or SPICE simulations to determine that
the overshoot and undershoot voltages are within the specifications.
When using a Stratix V device as a transmitter, you can use slow slew rate and series
termination to limit overshoot and undershoot at the I/O pins. Transmission line
effects that cause large voltage deviations at the receiver are associated with an
impedance mismatch between the driver and the transmission lines. By matching the
impedance of the driver to the characteristic impedance of the transmission line, you
can significantly reduce overshoot voltage. You can use a series termination resistor
placed physically close to the driver to match the total driver impedance to the
transmission line impedance. Stratix V devices support R
LVCMOS I/O standards in all I/O banks.
When using the Stratix V device as a receiver, you can use a clamping diode (off-chip)
if it is required to limit the overshoot voltage.
The 3.3-V I/O standard is supported using the bank supply voltage (V
and a V
sufficiently clamp overshoot voltage to within the DC and AC input voltage
specifications. The clamped voltage is expressed as the sum of the V
diode forward voltage.
In addition to the I/O registers in each IOE, Stratix V devices also have dedicated
registers and phase-shift circuitry on all I/O banks to interface with external memory.
Stratix V devices support new I/O standards such as SSTL-12, SSTL-15, SSTL-125,
SSTL-135, and HSUL-12.
Stratix V devices have the following dedicated circuitry for high-speed differential
I/O support:
■
■
■
■
■
■
■
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment
DPA
Synchronizer (FIFO buffer)
Phase-locked loops (PLLs)
CCPD
voltage of 3.0 V. In this method, the clamping diode (off-chip) can
CCIO
voltage is powered by 3.0 V.
IH
), and input low voltage (V
IL
) levels meet the 3.3-V I/O
Chapter 5: I/O Features in Stratix V Devices
OH
S
), output low voltage (V
OCT for all LVTTL and
May 2011 Altera Corporation
CCIO
CCIO
and the
) at 3.0 V
I/O Structure
OL
),