DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 358

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

12–2
Stratix V Programmable Power Technology
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Power consumption also affects thermal management. Stratix V devices offer a TSD
feature that self-monitors the device junction temperature and can be used with
external circuitry for other activities, such as controlling air flow to the Stratix V
FPGA.
This chapter contains the following sections:
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Stratix V devices offer the ability to configure portions of the core, called tiles, for
high-speed or low-power mode of operation performed by the Quartus II software
without user intervention. Setting a tile to high-speed or low-power mode is
accomplished with on-chip circuitry and does not require extra power supplies
brought into the Stratix V device. In a design compilation, the Quartus II software
determines whether a tile must be in high-speed or low-power mode based on the
timing constraints of the design.
A Stratix V tile consist of the following:
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All blocks and routing associated with the tile share the same setting of either
high-speed or low-power mode. By default, tiles that include DSP blocks or memory
blocks are set to high-speed mode for optimum performance. Unused DSP blocks and
memory blocks are set to low-power mode to minimize static power. Clock networks
do not support programmable power technology.
With programmable power technology, faster speed grade FPGAs may require less
power because there are fewer high-speed MLAB and LAB pairs, when compared
with slower speed grade FPGAs. The slower speed grade device may have to use
more high-speed MLAB and LAB pairs to meet performance requirements, while the
faster speed grade device can meet performance requirements with MLAB and LAB
pairs in low-power mode.
The Quartus II software sets unused device resources in the design to low-power
mode to reduce the static power. It also sets the following resources to low-power
mode when they are not used in the design:
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“Stratix V Programmable Power Technology”
“Stratix V External Power Supply Requirements”
“Temperature Sensing Diode”
Memory logic array block (MLAB)/logic array block (LAB) pairs with routing to
the pair
MLAB/LAB pairs with routing to the pair and to adjacent digital signal processing
(DSP)/memory block routing
TriMatrix memory blocks
DSP blocks
PCI Express
Physical Coding Sublayer (PCS)
LABs and MLABs
TriMatrix memory blocks
®
(PCIe) hard IP
Chapter 12: Power Management in Stratix V Devices
Stratix V Programmable Power Technology
May 2011 Altera Corporation