DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 87

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices
Adaptive Logic Modules
May 2011 Altera Corporation
You can implement any six-input function using inputs dataa, datab, datac, datad,
and either datae0 and dataf0 or datae1 and dataf1. If you use datae0 and dataf0, the
output is either driven to register0, or register0 is bypassed, or the output driven to
register0 and register0 is bypassed, and the data drives out to the interconnect
using the top set of output drivers
output either drives to register1 or bypasses register1 and drives to the
interconnect using the bottom set of output drivers. The Quartus II Compiler
automatically selects the inputs to the LUT. ALMs in normal mode support register
packing.
Figure 1–8. Input Function in Normal Mode
Notes to
(1) If you use datae1 and dataf1 as inputs to a six-input function, datae0 and dataf0 are available for register
(2) The dataf1 input is available for register packing only if the six-input function is unregistered.
Extended LUT Mode
Use extended LUT mode to implement a specific set of seven-input functions. The set
must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four
inputs.
extended LUT mode. In this mode, if the seven-input function is unregistered, the
unused eighth input is available for register packing.
Functions that fit into the template shown in
These functions often appear in designs as “if-else” statements in Verilog HDL or
VHDL code.
Figure 1–9. Template for Supported Seven-Input Functions in Extended LUT Mode
Note to
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second
packing.
register, reg1, is not available.
Figure
Figure
Figure 1–9
1–9:
1–8:
These inputs are available for register packing.
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
(1)
shows the template of supported seven-input functions using
datae0
datae1
dataf0
dataf1
dataa
datab
datac
datad
(2)
This input is available
for register packing.
5-Input
5-Input
LUT
LUT
6-Input
LUT
(Figure
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
labclk
combout0
(Note 1)
1–8). If you use datae1 and dataf1, the
Figure 1–9
D
reg0
D
D
reg0
reg1
Q
occur naturally in designs.
Q
Q
To general or
To general or
local routing
local routing
To general or
local routing
To general or
local routing
To general or
local routing
1–9