DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 331

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Remote System Upgrades
May 2011 Altera Corporation
1
1
Remote System Upgrade State Machine
After power-up, the shift register, control register, and update registers are reset to the
values listed in
configuration image is loaded. In the factory configuration image, the user logic
writes the AnF bit, page address, and watchdog timer settings for the next application
configuration image to the update register. When the logic array configuration reset
(RU_nCONFIG) goes low, the remote system upgrade state machine updates the
control register with the contents of the update register, and triggers a reconfiguration
to the new application configuration image.
If there is an error during reconfiguration to the new application configuration image,
the remote system upgrade state machine directs the system to re-load a factory
configuration image. The control and update registers are reset to POR reset values
and the status register is updated with the error information. For example, if there is a
CRC error during application configuration image configuration, the status register is
updated with 5'b00001.
If there is no error during reconfiguration and the application configuration image is
successfully loaded, the system stays in the application configuration image until
another reconfiguration trigger condition occurs. This can be a core nCONFIG
assertion, external nCONFIG assertion, or the watchdog timer time-out error. If this
happens, the control register and update registers are reset to POR reset values and
the status register is updated with the error information. Consequently, the system
proceeds to load the factory configuration image. Based on the status register content,
the user logic in the factory configuration image then decides to stay in the factory
configuration image or reload a new application reconfiguration image.
Read operations during factory configuration access the contents of the update
register. This feature is used by the factory configuration image user logic to verify
that the page address and watchdog timer settings are written correctly. Read
operations in application configurations access the contents of the control register.
This information is used by the user logic in the application configuration.
User Watchdog Timer
The user watchdog timer prevents a faulty application configuration from stalling the
device indefinitely. The system uses the timer to detect functional errors after an
application configuration is successfully loaded into the Stratix V device. This feature
is automatically disabled in the factory configuration image and enabled in the
application configuration image. Functional errors must not exist in the factory
configuration because they are stored and validated during production and must
never be updated remotely.
The user watchdog timer feature is automatically enabled in the application
configuration image. If you do not wish to use this feature, disable it during the
factory configuration image operation before triggering the reconfiguration to the
application configuration image.
Table
9–16, also known as POR reset values before the factory
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
9–51