DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 51

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Switching Characteristics
Table 2–26. High-Speed I/O Specifications for Stratix V Devices—Preliminary
May 2011 Altera Corporation
t
TCCS
Receiver
True Differential I/O
Standards -
f
f
DPA Mode
DPA run length
Soft CDR mode
Soft-CDR PPM
tolerance
Non DPA Mode
Sampling Window
Notes to
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) This only applies to LVDS source synchronous mode.
(4) This only applies to DPA and soft-CDR modes.
(5) Clock Boost Factor (W) is the ratio between the input data rate to the input clock rate.
(6) This is achieved by using the LVDS clock network.
(7) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local)
(8) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
(9) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew
(10) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
RISE &
HSDRDPA
HSDR
that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
(data rate)
Symbol
t
FALL
Table
(data rate)
2–26:
True Differential I/O Standards
Standards with Three External
True Differential I/O Standards
SERDES factor J = 3 to 10
SERDES factor J = 3 to 10
Output Resistor Networks
Emulated Differential I/O
Emulated Differential I/O
SERDES factor J = 2,
SERDES factor J = 1,
Uses DDR Registers
Uses SDR Register
Conditions
Standards
—
—
—
Min
150
—
—
—
—
—
—
—
(7)
(7)
(7)
–2 Speed Grade
Typ
—
—
—
—
—
—
—
—
—
—
—
10000
1434
Max
160
250
150
300
300
300
(9)
(7)
(7)
Stratix V Device Handbook Volume 1: Overview and Datasheet
Min
150
—
—
—
—
—
—
—
(7)
(7)
(7)
–3
(Note 1), (2), (3)
Speed Grade
Typ
—
—
—
—
—
—
—
—
—
—
—
10000
1250
Max
200
250
150
300
300
300
(9)
(7)
(7)
(Part 2 of 2)
Min
150
—
—
—
—
—
—
—
(7)
(7)
(7)
–4
Speed Grade
Typ
—
—
—
—
—
—
—
—
—
—
—
10000
1050
Max
200
300
150
300
300
300
(9)
(7)
(7)
2–23
Mbps
Mbps
Mbps
Mbps
PPM
Unit
ps
ps
ps
ps
ps
UI
±