DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 58

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Glossary
Glossary
Table 2–36. Glossary (Part 1 of 4)
May 2011 Altera Corporation
Letter
A
B
C
D
G
H
E
F
I
Differential I/O
Standards
f
f
f
HSCLK
HSDR
HSDRDPA
Subject
—
—
—
Table 2–36
Receiver Input Waveforms
Transmitter Output Waveforms
Left and right PLL input clock frequency.
High-speed I/O block—Maximum and minimum LVDS data transfer rate
(f
High-speed I/O block—Maximum and minimum LVDS data transfer rate
(f
Single-Ended Waveform
Differential Waveform
Single-Ended Waveform
Differential Waveform
HSDR
HSDRDPA
lists the glossary for this chapter.
= 1/TUI), non-DPA.
= 1/TUI), DPA.
V
V
CM
CM
V
V
ID
OD
V
V
ID
OD
Definitions
Stratix V Device Handbook Volume 1: Overview and Datasheet
—
—
—
V
V
ID
OD
p − n = 0 V
p − n = 0 V
Positive Channel (p) = V
Negative Channel (n) = V
Ground
Positive Channel (p) = V
Negative Channel (n) = V
Ground
IH
OH
IL
OL
2–30