DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 106

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–12
Figure 2–11. Mixed-Port Read-During-Write Timing Waveforms
Figure 2–12. True-Dual Port Memory for Stratix V Devices
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
wraddress
q (asynch)
True Dual-Port Mode
rdaddress
wrclock
rdclock
wren
data
rden
doutn-1
din-1
an-1
Figure 2–11
mode with unregistered outputs.
Stratix V M20K blocks support true dual-port mode. Sometimes called bidirectional
dual-port, this mode allows you to perform any combination of two port
operations—two reads, two writes, or one read and one write at two different clock
frequencies.
Figure 2–12
The widest bit configuration of the M20K blocks in true dual-port mode is 1k x 16-bit
(x20-bit with parity).
Wider configurations are unavailable because the number of output drivers is
equivalent to the maximum bit width of the respective memory block. Because true
dual-port RAM has outputs on two ports, its maximum width equals half of the total
number of output drivers.
bn
an
din
shows timing waveforms for read and write operations in mixed-port
shows the true dual-port RAM configuration.
doutn
data_a[]
address_a[]
wren_a
byteena_a[]
addressstall_a
rden_a
aclr_a
q_a[]
b0
clock_a
a0
a1
dout0
a2
b1
addressstall_b
address_b[]
byteena_b[]
data_b[]
clock_b
wren_b
rden_b
aclr_b
q_b[]
a3
Chapter 2: Memory Blocks in Stratix V Devices
din4
b2
a4
May 2011 Altera Corporation
din5
a5
b3
a6
din6
Memory Modes