DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 245

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
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SV51008-1.2
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
May 2011
May 2011
SV51008-1.2
f
This chapter describes external memory interfaces available with Stratix
as well as the silicon capabilities of Stratix V devices to support external memory
interfaces. Stratix V devices provide an efficient architecture to quickly and easily fit
wide external memory interfaces to support the high level of system bandwidth
within their small modular I/O bank structure. The I/Os are designed to provide
high-performance support for existing and emerging external double data rate (DDR)
memory standards, such as DDR3 and DDR2 SDRAM, QDR II+ and QDR II SRAM,
and RLDRAM II.
Stratix V I/O elements (IOEs) provide easy-to-use built-in functionality required for a
rapid and robust implementation with features such as dynamic calibrated on-chip
termination (OCT), trace mismatch compensation, read- and write-leveling support
for DDR3 SDRAM interfaces, read FIFO blocks, and 4- to 36-bit programmable DQ
group widths.
The high-performance memory interface solution includes the self-calibrating
UniPHY megafunction, which is optimized to take advantage of the Stratix V I/O
structure and the Quartus
the total solution for the highest reliable frequency of operation across process,
voltage, and temperature (PVT) variations.
This chapter contains the following sections:
■
■
For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to the
“Memory Interface Pin Support” on page 7–3
“Stratix V External Memory Interface Features” on page 7–8
External Memory Interface
®
II software TimeQuest Timing Analyzer, which provides
7. External Memory Interfaces in
Handbook.
Stratix V Devices
®
V devices,
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