DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 19

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Stratix V Device Family Overview
40G and 100G Ethernet Hard IP (Embedded HardCopy Block)
40G and 100G Ethernet Hard IP (Embedded HardCopy Block)
External Memory and General Purpose I/O
June 2011 Altera Corporation
The Stratix V GT, GX, and GS 40G and 100G Ethernet hard IP is standards-compliant
and proven. The hard IP includes 40GBASE-R PCS and XLAUI PMA for 40GE, and
100GBASE-R PCS and CAUI PMA for 100GE. The 40G and 100G Ethernet hard IP are
scalable because applications requiring multiple 40/100 GbE ports may use a single
PLL for the 40/100GBASE-R PCS instantiations to reduce FPGA core and clock
resources.
Furthermore, the integrated 10G transceiver simplifies multi-port 40/100GbE system
implementation by reducing chip count, board space, and power. Stratix V
transceivers interface directly with 40-Gbps QSFP and SFP, and 100-Gbps CFP
pluggable modules.
Stratix V devices offer high I/O bandwidth with up to seven 72-bit DDR3 SDRAM
memory interfaces running at 1,066 MHz/1,600 Mbps and LVDS running at 1.4 Gbps.
Each Stratix V I/O block has a hard FIFO that improves the resynchronization margin
as the data is transferred from memory to the FPGA. The hard FIFO also lowers PHY
latency, resulting in higher random access performance. General purpose I/Os
(GPIOs) include on-chip dynamic termination to reduce the number of external
components and minimize reflections. On-package decoupling capacitors suppress
noise on the power lines, which reduce noise coupling into the I/Os. Memory banks
are isolated to prevent core noise from coupling to the output, thus reducing jitter and
providing optimal signal integrity.
The external memory interface block also uses advanced calibration algorithms to
compensate for process, voltage and temperature (PVT) variations in the FPGA and
external memory components. The advanced algorithms ensure maximum
bandwidth and a robust timing margin across all conditions. Stratix V devices also
deliver a complete memory solution with the High Performance Memory
Controller II (HPMC II) and UniPHY MegaCore
advanced memory modules.
performance.
Table 1–8. External Memory Interface Performance
Note to
(1) The specifications listed in this table are performance targets. For a current achievable performance, use the
External Memory Interface Spec
Table
1–8:
RLDRAM III
RLDRAM II
Interface
QDR II+
QDR II
DDR3
DDR2
Estimator.
Table 1–8
lists external memory interface block
(Note 1)
®
IP that simplify a design for today’s
Performance (MHz)
1,066
533
350
550
533
800
Stratix V Device Handbook
1–13