DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 216

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

6–2
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
For high-speed differential interfaces, the Stratix V device family supports the
following differential I/O standards:
■
■
■
Stratix V devices support ubiquitous I/Os. Row and column I/Os support the same
features.
Figure 6–1. I/O Bank Support in the Stratix V Device Family
Notes to
(1) All I/O banks support LVDS, RSDS, and mini-LVDS I/O standards using true LVDS output buffers without resistor
(2) All I/O banks support RSDS and mini-LVDS I/O standards using two single-ended output buffers with a
(3) 100- differential input termination (R
(4) The ALTLVDS Use External PLL option will only be available in future Quartus II software releases.
The ALTLVDS transmitter and receiver requires various clock and load enable signals
from a fractional PLL. The Quartus
automatically. It is also responsible for generating the various clock and load enable
signals based on the input reference clock and selected data rate.
LVDS
Mini-LVDS
Reduced swing differential signaling (RSDS)
networks.
three-resistor (RSDS_E_3R and mini-LVDS_E_3R) network.
Figure
Figure 6–1
6–1:
with 'Use External PLL'
Option Enabled (4)
LVDS Interface
shows I/O bank support for the Stratix V device family.
Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
D
OCT) is supported in all I/O banks.
®
SERDES Circuitry
II software configures the PLL settings
LVDS I/Os
Dedicated
I/Os with
(Note
with 'Use External PLL'
Option Disabled (4)
LVDS Interface
1), (2),
May 2011 Altera Corporation
(3)
Overview