DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 479

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
PCI Express (PCIe)—Gen1 and Gen2
Figure 4–14. Example of PIPE ×4 Channel Placement Using the CMU PLL
Notes to
(1) Channels shaded in blue provide the high-speed serial clock.
(2) Channels shaded in gray are data channels.
(3) The Quartus II software automatically places the clock generator and master channel in either channel 1 or channel 4 within a transceiver bank.
Figure 4–15. Example of PIPE ×8 Channel Placement Using a CMU PLL
Notes to
(1) Channels shaded in blue provide the serial clock.
(2) Channels shaded in gray are data channels.
May 2011 Altera Corporation
PCI Express PHY (PIPE) ×8
Figure
Figure
4–14:
4–15:
Stratix V Device
Transceiver Bank
Transceiver Bank
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
PCI Express PHY (PIPE) ×4
PCI Express PHY (PIPE) ×4
CMU PLL
Master
Transceiver Bank
Transceiver Bank
Transceiver Bank
Transceiver Bank
Stratix V Device
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
CMU PLL
Master
CMU PLL
CMU PLL
Master
Master
PCI Express
PHY (PIPE) ×8
PCI Express
PHY (PIPE) ×8
Transceiver Bank
Transceiver Bank
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Stratix V Device
Transceiver Bank
Transceiver Bank
CMU PLL
CMU PLL
Master
Master
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
(Note
(Note
CMU PLL
Master
1),
Stratix V Device Handbook Volume 3: Transceivers
1), (2),
(2)
PCI Express PHY (PIPE) ×4
PCI Express PHY (PIPE) ×4
(3)
Transceiver Bank
Transceiver Bank
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
CMU PLL
Master
PCI Express PHY (PIPE) ×8
4–23