DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 309

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Passive Serial Configuration
Figure 9–16. PS Multi-device Configuration when Both Devices Receive Different Sets of Configuration Data
Notes to
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. V
(2) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device’s nCE pin.
(3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL, refer to
Figure 9–17. PS Multi-device Configuration When Both Devices Receive the Same Set of Configuration Data
Notes to
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. V
(2) You can leave the nCEO pin unconnected or use it as a user I/O pin.
(3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL, refer to
May 2011 Altera Corporation
specification of the I/O on the device and the external host. Altera recommends powering up all the configuration system I/Os with V
specification of the I/O on the device and the external host. Altera recommends powering up all the configuration system I/Os with V
Figure
Figure
(MAX II Device or
(MAX II Device or
Microprocessor)
9–16:
Microprocessor)
9–17:
External Host
External Host
ADDR
ADDR
Memory
Memory
Figure 9–16
devices in the chain receive different sets of configuration data (multiple .sofs).
In
configuration chain, its nCEO pin drives low to activate the second device’s nCE pin,
which prompts the second device to begin configuration. The second device in the
chain begins configuration in one clock cycle; therefore, the transfer of data to the
second device is transparent to the external host.
Figure 9–17
same set of configuration data (single .sof).
DATA0
DATA0
Figure
9–16, after the first device completes configuration in a multi-device
10 k
10 k
V
V
CCPGM(1)
CCPGM(1)
shows the PS multi-device configuration using an external host when all
shows the PS multi-device configuration when all devices receive the
10 k
10 k
V
V
CCPGM(1)
CCPGM(1)
GND
GND
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix V Device 1
Stratix V Device 1
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
MSEL[4..0]
MSEL[4..0]
nCEO
nCEO
N.C.
(3)
(3)
(2)
GND
CCPGM
CCPGM
must be high enough to meet the V
must be high enough to meet the V
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix V Device 2
Stratix V Device 2
MSEL[4..0]
Table 9–4 on page
MSEL[4..0]
Table 9–4 on page
nCEO
nCEO
N.C.
N.C. (2)
(3)
(3)
(2)
CCPGM
CCPGM
9–7.
9–7.
.
.
9–29
IH
IH