DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 487

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
GIGE
Figure 4–21. GIGE Mode for Stratix V Devices
May 2011 Altera Corporation
Transceiver Datapath Configuration
Figure 4–21
configuration. Blocks shown as “Disabled” are not used, but incur latency. Blocks
shown as “Bypassed” are not used and do not incur any latency.
Transceiver PHY IP
Lane Data Rate
Number of Bonded Channels
Low-Latency PCS
Word Aligner
(Pattern Length)
Rate Match FIFO
8B/10B Encoder/Decoder
Byte SERDES
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency
shows the transceiver blocks and settings enabled in a GIGE
Synchronization
Custom PHY IP
(7-Bit Comma,
State Machine
(GIGE Preset)
10-Bit/K28.5/)
1-Bit Control
Stratix V Device Handbook Volume 3: Transceivers
8-Bit Data
1.25 Gbps
Automatic
125 MHz
Disabled
Disabled
Disabled
Enabled
Enabled
None
4–31