DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 297

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Active Serial Configuration (Serial Configuration Devices)
May 2011 Altera Corporation
1
1
1
Table 9–9
Table 9–9. DCLK Frequency Specification in the AS Configuration Scheme
You can choose the internal oscillator or CLKUSR as the DCLK clock source by selecting
the option under Device and Pins Option settings, Configuration panel in the
Quartus II software. This sets specific option in the programming file. By default, in
AS scheme, Stratix V devices power-up and begin configuration with 12.5 MHz
internal oscillator as the DCLK clock source. After reading the option bits from the
programming file, Stratix V devices continue using the internal oscillator at
12.5 MHz frequency, switch to a higher internal oscillator clock frequency, or switch to
the CLKUSR pin.
If you choose CLKUSR as configuration clock source, the maximum frequency allowed
is 100 MHz.
During device configuration, Stratix V devices read the configuration data using the
serial interface, decompress the data if necessary, and configure their SRAM cells. In
the AS scheme, the Stratix V device controls the configuration interface. In the PS
scheme, the external host (a MAX II device or microprocessor) controls the interface.
You can select between the AS ×1 and AS ×4 settings by selecting the option under
Device and Pins Option settings, Configuration panel in the Quartus II software.
This sets a specific option bit in the programming file. By default, in the AS scheme,
Stratix V devices power-up and begin configuration as an AS ×1 mode. Upon reading
the option bits from the programming file, Stratix V devices either stay as an AS ×1
mode or switch to an AS ×4 mode for the rest of the configuration.
Notes to
(1) This information is preliminary.
(2) This applies to the DCLK frequency specification when using the internal oscillator as the configuration clock
source.
Minimum
Table
10.6
21.3
42.6
5.3
lists the DCLK frequency specification in the AS configuration scheme.
9–9:
Typical
15.7
31.4
62.9
7.9
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Maximum
100.0
12.5
25.0
50.0
(Note
1),
Unit
MHz
MHz
MHz
MHz
(2)
9–17