DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 454

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

3–6
Stratix V Device Handbook Volume 3: Transceivers
Figure 3–3. Transceiver Reset Sequence Timing Diagram for CDR in Manual Lock Mode
Notes to
(1) t
(2) reconfig_busy is driven from the transceiver reconfiguration controller.
pll_powerdown
Stratix V Device Power Up
Figure
phy_mgmt_clk_reset
Control Signals
rx_is_lockedtoref[0]
reconfig_busy (2)
rx _ set_locktodata
Status Signals
3–3:
, t
rx _ set_locktoref
pll_powerdown
rx _ analogreset
tx_digitalreset
LTD_Manual
rx _ digitalreset
pll_is_locked
rx_ready
tx_ready
, and t
LTR_LTD_Manual
t
pll_powerdown
are pending characterization.
Chapter 3: Transceiver Reset Control in Stratix V Devices
(1)
clock cycles
two parallel
t
LTR_LTD_Manual
May 2011 Altera Corporation
Transceiver Reset Sequence
t
LTD_Manual
(1)
(1)