DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 47

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Switching Characteristics
Table 2–21. PLL Specifications for Stratix V Devices (Part 3 of 3)—Preliminary
Table 2–22. Block Performance Specifications for Stratix V DSP Devices—Preliminary
May 2011 Altera Corporation
f
Notes to
(1) Pending silicon characterization.
(2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
(3) This specification is limited by the lower of the two: I/O F
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source < 120 ps.
(5) F
(6) Peak-to-peak jitter with a probability level of 10
(7) The cascaded PLL specification is only applicable with the following condition:
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) The external memory interface clock output jitter specifications use a different measurement method, which is available in
Three 9 × 9
One 18 × 18
Two partial 18 × 18 (or 16 × 16)
One 27 × 27
One 36 × 18
One sum of two 18 × 18 (One sum of two 16 × 16)
One sum of square
One 18 × 18 plus 36 (a × b) + c
Three 18 × 18
One sum of four 18 × 18
One sum of two 27 × 27
One sum of two 36 × 18
One complex 18 × 18
One 36 × 36
One complex 18 × 25
RES
Symbol
standard.
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in
a. Upstream PLL: 0.59Mhz  Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
page
REF
Table
is fIN/N when N = 1.
2–27.
2–21:
Resolution of VCO frequency (f
DSP Block Specifications
Table 2–22
Mode
Modes using One DSP
Modes using Two DSPs
Modes using Three DSPs
lists the Stratix V DSP block performance specifications.
Parameter
–12
(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
INPFD
Table 2–33 on page
MAX
= 100 MHz)
or F
OUT
Speed Grade
of the PLL.
600
600
600
450
450
500
450
500
500
425
425
425
500
400
350
–2
2–28.
Stratix V Device Handbook Volume 1: Overview and Datasheet
Performance
Speed Grade
Min
—
480
480
480
360
360
400
360
400
400
340
340
340
400
320
280
–3
(Note 1)
5.96
Typ
(Note 1)
Speed Grade
420
420
420
315
315
350
315
350
350
298
298
298
350
280
245
–4
(Part 1 of 2)
Max
—
Table 2–31 on
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
Hz
2–19