DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 313

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Passive Serial Configuration
Figure 9–20. Multi-Device PS Configuration Using an Altera Download Cable
Notes to
(1) Connect the pull-up resistor to the same supply voltage (V
(2) You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures
(3) In the USB-Blaster and ByteBlaster II cables, this pin is connected to nCE when you use it for AS programming; otherwise, it is a no connect.
(4) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[4..0], refer to
May 2011 Altera Corporation
that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need the pull-up
resistors on DATA0 and DCLK.
page
Figure
9–7.
Multi-Device PS Configuration Using Download Cable
9–20:
10 kΩ
V
CCPGM
10 kΩ
V
CCPGM
You can use a download cable to configure multiple Stratix V devices as shown in
Figure
In
to activate the second device’s nCE pin, which prompts the second device to begin
configuration. The nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE pins are
connected to every device in the chain. As all the CONF_DONE and nSTATUS pins are
tied together, all devices initialize and enter user mode at the same time. If any device
detects an error, configuration stops for the entire chain and you must reconfigure all
the devices. For example, if the first device flags an error on nSTATUS, it resets the
chain by pulling its nSTATUS pin low. This behavior is similar to a single device
detecting an error.
(1)
Figure
(2)
(1)
9–20.
GND
9–20, after the first device completes configuration, its nCEO pin drives low
(4)
(4)
DATA0
nCONFIG
nCONFIG
Stratix V Device 1
nCE
MSEL[4..0]
nCE
MSEL[4..0]
DATA0
Stratix V Device 2
CONF_DONE
CONF_DONE
nSTATUS
nSTATUS
CCIO
DCLK
nCEO
nCEO
DCLK
) as the USB-Blaster, ByteBlaster II, or EthernetBlaster cable.
10 kΩ
V
N.C.
CCPGM
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
V
(1)
CCPGM
10 kΩ
(1)
10 kΩ
V
CCPGM
(2)
(1)
10-Pin Male Header
Pin 1
Download Cable
(PS Mode)
GND
V
CCPGM
V
GND
IO
(1)
(3)
Table 9–4 on
9–33