DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 406

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–34
Figure 1–30. Receiver Gear Box
Stratix V Device Handbook Volume 3: Transceivers
66-Bit in 10GBASE-R
Receiver 10G PCS Datapath
67-Bit in Interlaken
The receiver channel datapath shown in
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■
■
■
■
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Receiver Gear Box
The receiver gear box adapts the PMA data width to a larger bus width so for
interfacing with the PCS.
The PMA bus width is smaller than the PCS bus width, so the receiver gear box
expands the data bus width from the PMA to the PCS. Because this process is
transparent, you can continuously feed data to the receiver gear box.
shows the receiver gear box for the 10GBASE-R configuration.
In addition to providing the bus width adaptation, the receiver gear box provides the
receiver bit reversal feature.
Receiver Bit Reversal
The receiver gear box allows bit reversal of received data. This feature is similar to the
transmitter bit reversal feature. Some protocols, such as Interlaken, require the bit
reversal feature. For more information, refer to
page
“Receiver Gear Box” on page 1–34
“Block Synchronizer” on page 1–35
“Disparity Checker” on page 1–35
“Descrambler” on page 1–35
“Frame Synchronizer” on page 1–36
“Bit-Error Rate (BER) Monitor” on page 1–37
“64B/66B Decoder” on page 1–37
“CRC-32 Checker” on page 1–37
“Receiver FIFO” on page 1–37
1–17.
RX Gear Box
Reversal
RX
Bit
Receiver Channel PMA
40-Bit Data from
Figure 1–29
Chapter 1: Transceiver Architecture in Stratix V Devices
Loopback
“Transmitter Bit Reversal” on
consists of the following blocks:
From Receiver Deserializer
From Transmitter Gear Box
May 2011 Altera Corporation
Figure 1–30
10G PCS Architecture