DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 226

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

6–12
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
1
The fractional PLL receives the external clock input and generates different phases of
the same clock. The DPA block chooses one of the clocks from the fractional PLL and
aligns the incoming data on each channel. The synchronizer circuit is a 1-bit wide by
6-bit deep FIFO buffer that compensates for any phase difference between the DPA
clock and the data realignment block. If necessary, the user-controlled data
realignment circuitry inserts a single bit of latency in the serial bit stream to align to
the word boundary. The deserializer includes shift registers and parallel load
registers, and sends a maximum of 10 bits to the internal logic.
The Stratix V device family supports three different receiver modes:
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■
■
The physical medium connecting the transmitter and receiver LVDS channels may
introduce skew between the serial data and the source-synchronous clock. The
instantaneous skew between each LVDS channel and the clock also varies with the
jitter on the data and clock signals as seen by the receiver. The three different modes—
non-DPA, DPA, and soft-CDR—provide different options to overcome skew between
the source synchronous clock (non-DPA, DPA) /reference clock (soft-CDR) and the
serial data.
Only the non-DPA mode requires manual skew adjustment.
“Non-DPA Mode” on page 6–18
“DPA Mode” on page 6–19
“Soft-CDR Mode” on page 6–20
Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
May 2011 Altera Corporation
Differential Receiver