DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 298

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–18
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Figure 9–6
Figure 9–6. Single Device AS ×1 Mode Configuration
Notes to
(1) Connect the pull-up resistors to V
(2) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL, refer to
(3) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The maximum
Table 9–4 on page
frequency specification is 100 MHz.
Figure
Serial Configuration
shows the single-device configuration setup for an AS ×1 mode.
Device
9–6:
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
9–7.
DATA
DCLK
ASDI
nCS
V
CCPGM (1)
CCPGM
10 kΩ
V
CCPGM (1)
at 3.0-V supply.
10 kΩ
V
CCPGM (1)
GND
10 kΩ
Active Serial Configuration (Serial Configuration Devices)
nCONFIG
nSTATUS
CONF_DONE
nCE
AS_DATA1
DCLK
nCSO
ASDO
Stratix V Device
MSEL[4..0]
CLKUSR
nCEO
May 2011 Altera Corporation
N.C.
(2)
(3)