DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 201

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: I/O Features in Stratix V Devices
Termination Schemes for I/O Standards
Figure 5–12. OCT User-Mode Signal Timing Waveform for Two OCT Blocks
Notes to
(1) ts2p  25 ns
(2) S2PENA_1A is asserted in Bank 1A for calibration block 0.
(3) S2PENA_2A is asserted in Bank 2A for calibration block 1.
Termination Schemes for I/O Standards
May 2011 Altera Corporation
Figure
Single-Ended I/O Standards Termination
S2PENA_1A (2)
S2PENA_2A (3)
OCTUSRCLK
5–12:
ENASER0
ENASER1
nCLRUSR
ENAOCT
Example of Using Multiple OCT Calibration Blocks
Figure 5–12
and R
asserting the ENASER signals at different times. ENAOCT must remain asserted while any
calibration is ongoing. You must set nCLRUSR low for one OCTUSRCLK cycle before each
ENASER[N] signal is asserted. In
time to initialize OCT calibration block 0, this does not affect OCT calibration block 1,
whose calibration is already in progress.
The following sections describe the different termination schemes for the I/O
standards used in Stratix V devices.
Voltage-referenced I/O standards require both an input reference voltage (V
a termination voltage (V
termination voltage of the transmitting device.
The supported I/O standards such as SSTL-15, SSTL-135, SSTL-125, and SSTL-12
typically do not require external board termination. Altera recommends using
dynamic OCT with these I/O standards to save board space and cost by reducing the
number of external termination resistors used.
T
calibration. Calibration blocks can start calibrating at different times by
shows a signal timing waveform for two OCT calibration blocks doing R
1000
CY CLE S
OCTUSRCLK
Calibration Phase
1000
CY CLE S
TT
OCTUSRCLK
). The reference voltage of the receiving device tracks the
Figure
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
5–12, when you set nCLRUSR to 0 for the second
32
OCTUSRCLK
CY CLE S
ts2p (1)
32
OCTUSRCLK
CY CLE S
ts2p (1)
REF
) and
5–25
S