DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 199

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: I/O Features in Stratix V Devices
OCT Calibration
May 2011 Altera Corporation
1
Figure 5–10
blocks are in calibration mode; when ENAOCT is 0, all OCT calibration blocks are in
serial data transfer mode. The OCTUSRCLK clock frequency must be 20 MHz or less.
You must generate all user signals on the rising edge of the OCTUSRCLK signal.
Figure 5–10. Signals Used for User Mode Calibration
OCT Calibration
Figure 5–11
(where N is a calibration block number), you must assert ENAOCT one cycle before
asserting ENASER[N]. Also, nCLRUSR must be set to low for one OCTUSRCLK cycle before
the ENASER[N] signal is asserted. Assert the ENASER[N] signals for 1000 OCTUSRCLK
cycles to perform R
cycle after the last ENASER is deasserted.
shows user mode signal-timing waveforms. To calibrate OCT block[N]
shows the flow of the user signal. When ENAOCT is 1, all OCT calibration
S
OCT and R
CB8
CB3
T
OCT calibration. You can deassert ENAOCT one clock
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
OCTUSRCLK,
ENASER[N]
ENAOCT, nCLRUSR,
Stratix V
Core
S2PENA_4C
S2PENA_6C
CB7
CB4
CB6
CB5
5–23