DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 192

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–16
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Figure 5–3
R
is no longer selectable.
Figure 5–3. R
To use OCT for the SSTL Class I I/O standard, you must select the 50-  R
setting, thus eliminating the external 25-  R
For the SSTL Class II I/O standard, you must select the 25-  R
match the 50-  transmission line and the near-end external 50-  pull-up to V
R
Stratix V devices support R
calibration circuit compares the total impedance of the I/O buffer to the external
240-  or 100-  reference resistor connected to the RZQ pin and dynamically enables or
disables the transistors until they match.
The R
occurs at the end of device configuration. When the calibration circuit finds the
correct impedance, it powers down and stops changing the characteristics of the
drivers.
Figure 5–4. R
S
S
values are 25  and 50  . When you select matching impedance, current strength
OCT with Calibration
S
shown in
shows the R
S
S
OCT Without Calibration
OCT with Calibration
Series Termination
Series Termination
Figure 5–4
Stratix V Driver
Stratix V Driver
S
as the intrinsic impedance of the output transistors. Typical
S
V
V
is the intrinsic impedance of the transistors. Calibration
GND
GND
CCIO
CCIO
OCT with calibration in all banks. The R
R
R
R
R
S
S
S
S
Z
Z
0
0
= 50 Ω
= 50 Ω
S
(to match the 50-  transmission line).
Chapter 5: I/O Features in Stratix V Devices
OCT Support and I/O Termination Schemes
Receiving
Receiving
Device
Device
S
May 2011 Altera Corporation
OCT setting (to
S
OCT
S
OCT
TT
).