DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 468

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–12
Stratix V Device Handbook Volume 3: Transceivers
The frame synchronizer features a whole set of error and performance monitoring
ports to the FPGA fabric interface and register status bits when using the Avalon
Memory-Mapped Management Interface. A receiver ready port, frame lock status,
and cyclic redundancy check (CRC)-32 error detection port is available to the FPGA
fabric. The Avalon Memory-Mapped Management Interface provides additional
functionality with word boundary lock, frame lock status, synchronization word error
detection, scrambler mismatch error, and CRC-32 error detection status register bits.
Clock Compensation for Repeater Applications
The receiver FIFO in the receiver Interlaken PCS datapath is capable of compensating
a ±100 PPM difference between the remote transmitter and the local receiver using
metaframe lengths between 5 to 8191 words. Interlaken employs clock compensation
for repeater applications by inserting skip words on the egress traffic and silently
deleting skip words on the ingress traffic, depending on the PPM difference.
Skip Word Insertion
The frame generator generates the mandatory skip words with every metaframe
following the scrambler state word for clock rate compensation and generates
additional skip words based on the transmit FIFO capacity state.
Skip Word Deletion
The frame synchronizer silently discards the skip words it receives.
Diagnostic Word Generation and Checking of Lane Data Integrity (CRC-32)
The CRC-32 generator calculates the CRC for each metaframe and appends it to the
diagnostic word of the metaframe. The CRC-32 checker, in addition to checking for
lane CRC-32 errors, also retrieves the lane status message in the bit-33 location and
link status message in the bit-32 location of the diagnostic word. A CRC-32 error flag
is also provided to the FPGA fabric.
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
May 2011 Altera Corporation
Interlaken
®