DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 232

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

6–18
Figure 6–17. Receiver Datapath in Non-DPA Mode
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
Receiver Datapath Modes
6–17:
10
The Stratix V device family supports three receiver datapath modes: non-DPA mode,
DPA mode, and soft-CDR mode.
Non-DPA Mode
Figure 6–17
and synchronizer blocks are disabled. Input serial data is registered at the rising or
falling edge of the serial LVDS_diffioclk clock produced by the left and right PLLs.
You can select the rising/falling edge option using the ALTLDVS MegaWizard
Plug-In Manager. Both data realignment and deserializer blocks are clocked by the
LVDS_diffioclk clock, which is generated by the left and right PLLs.
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
shows the non-DPA datapath block diagram. In non-DPA mode, the DPA
IOE
2
Fractional PLL
3
DOUT DIN
Clock Mux
Bit Slip
(Note
(LVDS_LOAD_EN,
LVDS_diffioclk,
Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
rx_outclk)
diffioclk
1), (2),
rx_inclock
(3)
8 Serial LVDS
Clock Phases
Synchronizer
DOUT DIN
L L
LVDS Receiver
N
3
(DPA_LO
DPA_diffioclk,
rx_divfwdclk)
P P
P P
AD_EN,
May 2011 Altera Corporation
DPA Circuitr
Retimed
DPA Cloc
LVDS Clock Domain
P P
P P
Data
k
DIN
Differential Receiver
y
+
rx_in