DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 111

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Memory Blocks in Stratix V Devices
Design Considerations
Design Considerations
May 2011 Altera Corporation
Single Clock Mode
Selecting Embedded Memory Blocks
Conflict Resolution
Read-During-Write Behavior
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When using read/write clock mode, if you perform a simultaneous read/write to the
same address location, the output read data is unknown. If you require the output
data to be a known value, use either single-clock mode or input/output clock mode
and choose the appropriate read-during-write behavior in the MegaWizard Plug-In
Manager.
Stratix V embedded memory blocks can implement single-clock mode for true
dual-port, simple dual-port, and single-port memories. In this mode, a single clock,
together with a clock enable, controls all registers of the memory block. Asynchronous
clears are available on output latches and output registers only.
This section describes guidelines for designing with embedded memory blocks.
The Quartus II software automatically partitions user-defined memory into
embedded memory blocks by taking into account both speed and size constraints
placed on your design. For example, the Quartus II software may spread memory out
across multiple memory blocks when resources are available to increase the
performance of the design. You can manually assign memory to a specific block size
using the RAM MegaWizard Plug-In Manager.
MLABs can implement single-port SRAM through emulation with the Quartus II
software. Emulation results in minimal additional logic resources used. Because of the
dual-purpose architecture of the MLAB, it only has data input registers and output
registers in the block. MLABs gain read address registers from ALMs, while the write
address and read data registers are internal to MLAB.
For more information about register packing, refer to the
Adaptive Logic Modules in Stratix V Devices
When using memory blocks in true dual-port mode, you can perform two write
operations to the same memory location (address). Because there is no conflict
resolution circuitry in the memory blocks, you must implement conflict resolution
logic external to the memory block to avoid unknown data being written to the
address.
You can customize the read-during-write behavior of the Stratix V embedded
memory blocks to suit your design requirements. There are two types of
read-during-write operations—same port and mixed port.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
chapter.
Logic Array Blocks and
2–17