DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 418

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–2
Stratix V Device Handbook Volume 3: Transceivers
Input Reference Clock Sources
The transceiver channel PLL and ATX PLL derive the input clock from a dedicated
refclk pin, a fractional PLL, or through the reference clock network.
shows an overview of the input reference clock input to the transceiver channel.
Figure 2–2. Input Reference Clock Sources to Transceiver Channel
Table 2–1
PLLs.
Table 2–1. Input Reference Clock Source Performance
Notes to
(1) 1 indicates the best jitter performance.
(2) The performance is pending characterization.
Dedicated
refclk
pin
Table
lists the jitter performance of the input reference clock resources for transmit
2–1:
Reference Clock Source
Reference clock network
Dedicated refclk pin
Reference Clock
Fractional PLL
Network
Fractional
PLL
Chapter 2: Transceiver Clocking in Stratix V Devices
Clock
Input
(Note
1),
(CMU PLL/CDR)
Channel PLL
(2)
or ATX PLL
Jitter Performance
May 2011 Altera Corporation
Input Reference Clocking
Figure 2–2
1
2
3
Serial Clock