DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 525

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 6: Transceiver Loopback Support in Stratix V Devices
Reverse Serial Loopback
Figure 6–2. PCIe Reverse Parallel Loopback Configuration Datapath
Note to
(1) Grayed-out blocks are not active in this configuration.
Reverse Serial Loopback
Figure 6–3. Reverse Serial Loopback Datapath
Note to
(1) Grayed-out blocks are not active in this configuration.
May 2011 Altera Corporation
Fabric
FPGA
Fabric
FPGA
Figure
Figure
6–2:
6–3:
Reverse serial loopback is available as a subprotocol under custom configuration. In
reverse serial loopback, the data is received through the rx_serial_data port,
retimed through the receiver CDR, and sent out to the tx_serial_data port. The
received data is also available to the FPGA logic. No dynamic pin control is available
to select or deselect reverse serial loopback.
datapath for reverse serial loopback mode.
The active block of the transmitter channel is only the transmitter buffer. You can
change the V
through the ALTGX MegaWizard
reconfiguration controller. Reverse serial loopback is often implemented when using a
bit error rate tester (BERT) on the upstream transmitter.
Compensation
wrclk
TX Phase
OD
FIFO
rdclk
and the pre-emphasis first post tap values on the transmitter buffer
Transmitter PCS
Receiver PCS
(Note 1)
wrclk
Byte Serializer
Transmitter PCS
Receiver PCS
rdclk
™
Plug-In Manager or through the dynamic
(Note 1)
Figure 6–3
8B10B Encoder
Stratix V Device Handbook Volume 3: Transceivers
shows the transceiver channel
Reverse Parallel
Loopback Path
Transmitter PMA
Receiver PMA
Transmitter PMA
Receiver PMA
6–3