DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 314

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–34
JTAG Configuration
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
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You can use the same JTAG interface specifically developed for boundary-scan test
(BST) to shift the configuration data into the device. The Quartus II software
automatically generates a .sof that you can use for JTAG configuration with a
download cable in the Quartus II software programmer.
For more information about JTAG BST and the commands available using Stratix V
devices, refer to the following documents:
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Stratix V devices are designed such that JTAG instructions have precedence over any
device configuration modes. JTAG configuration can take place without waiting for
other configuration modes to complete. For example, if you attempt JTAG
configuration of Stratix V devices during a PS configuration, the PS configuration is
terminated and the JTAG configuration begins. All user I/O pins are tri-stated during
the JTAG configuration.
You cannot use the Stratix V decompression or design security features if you are
configuring your Stratix V device using JTAG-based configuration.
For more information about TDI, TDO, TMS, and TCK, refer to
Pins” on page
For instructions to connect a JTAG chain with multiple voltages across the devices in
the chain, refer to the
To configure a single device in a JTAG chain, the programming software places all the
other devices in bypass mode. In bypass mode, devices pass programming data from
the TDI pin to the TDO pin through a single bypass register without being affected
internally. This scheme enables the programming software to program or verify the
target device. Configuration data driven into the device appears on the TDO pin one
clock cycle later. The Quartus II software verifies successful JTAG configuration after
completion by checking the state of CONF_DONE through the JTAG port.
If CONF_DONE is not high, the Quartus II software indicates that configuration has
failed. If CONF_DONE is high, the software indicates that configuration was successful.
After the configuration data is transmitted serially using the JTAG TDI port, the TCK
port is clocked an additional 1,222 cycles to perform device initialization.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on
Stratix V devices do not affect JTAG boundary-scan or programming operations.
You can generate a JAM File (.jam) or Jam-byte Code (.jbc) to be used with other third
party programmer tools. Alternatively, you can use JRunner with .rbf to program
your device.
JTAG Boundary-Scan Testing in Stratix V Devices
Programming Support for Jam STAPL Language
9–38.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
JTAG Boundary Scan Testing in Stratix V Devices
chapter
“Device Configuration
May 2011 Altera Corporation
chapter.
JTAG Configuration