DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 197

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DK-DEV-5SGXEA7/ES

Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Datasheets

Specifications of DK-DEV-5SGXEA7/ES

Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
Chapter 5: I/O Features in Stratix V Devices
OCT Calibration
Figure 5–9. Example of Calibrating Multiple I/O Banks with One Shared OCT Calibration Block—Preliminary
May 2011 Altera Corporation
1
Sharing an OCT Calibration Block on Multiple I/O Banks
An OCT calibration block has the same V
OCT calibration is supported on all I/O banks with different V
standards, up to the number of available OCT calibration blocks. You can configure
the I/O banks to receive calibration codes from any OCT calibration block with the
same V
even if that particular I/O bank has an OCT calibration block.
For example,
If a group of I/O banks has the same V
block to calibrate the group of I/O banks placed around the periphery. Because 3B,
4C, 6C, and 7B have the same V
(3B, 4C, 6C, and 7B) with the OCT calibration block (CB7) located in bank 7A. You can
enable this by serially shifting out the R
calibration block located in bank 7A to the I/O banks located around the periphery.
I/O banks that do not contain calibration blocks share calibration blocks with I/O
banks that contains calibration blocks.
Figure 5–9
chip packages. This figure does not show transceiver calibration blocks.
Bank 8A
Bank 3A
CCIO
Bank 8B
Bank 3B
is a top view of the silicon die that corresponds to a reverse view for flip
. All I/O banks with the same V
Figure 5–9
Bank 3C
Bank 8C
This is a top view of the silicon die that corresponds to a reverse view for
flip chip packages. This figure illustrates the highest density for Stratix V devices.
More information about other Stratix V devices bank locations will be
available in future releases of the Stratix V device pin-out files.
Bank 8D
Bank 3D
shows a group of I/O banks that has the same V
Bank 8E
Bank 3E
CCIO
Bank 4E
Bank 7E
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
as bank 7A, you can calibrate all four I/O banks
CCIO
Bank 7D
Bank 4D
S
CCIO
OCT calibration codes from the OCT
CCIO
voltage, you can use one OCT calibration
Bank 7C
Bank 4C
as the I/O bank that contains the block.
I/O bank with the same V
I/O bank with different V
can share one OCT calibration block,
Bank 7B
Bank 4B
Bank 7A
Bank 4A
CCIO
CB7
CCIO
CCIO
voltage
CCIO
voltage.
5–21

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