DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 125

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 3: Variable Precision DSP Blocks in Stratix V Devices
Operational Mode Descriptions
Operational Mode Descriptions
May 2011 Altera Corporation
Output Register Bank
Independent Multiplier Modes
The positive edge of the clock signal triggers the 64-bit bypassable output register
bank and is cleared after power up. The following variable precision DSP block
signals control the output register per variable precision DSP block:
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This section describes how you can configure a Stratix V variable precision DSP block
to efficiently support the following operational modes:
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■
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In independent input and output multiplier mode, the variable precision DSP blocks
perform individual multiplication operations for general purpose multipliers.
9 x 9, 16 x 16, 18 x18, 27 x 27, and 36 x 18 Multipliers
You can configure each variable precision DSP block multiplier for 9-, 16-, 18-, 27-bit,
or 36 x 18 multiplication. A variable precision DSP block can support up to three
individual 9 x 9 multipliers, two individual 16 × 16 multipliers, two individual 18 x 18
partial multipliers, one individual 18 x 18 multiplier, one individual 27 x 27
multiplier, or one individual 36 x 18 multiplier. For some operational modes, the
unused inputs require zero padding.
CLK[2..0]
ENA[2..0]
ACLR[1]
“Independent Multiplier Modes” on page 3–9
“Independent Complex Multiplier Modes” on page 3–14
“Multiplier Adder Sum Mode” on page 3–17
“Sum of Square Mode” on page 3–20
“18 x 18 Multiplication Summed with 36-Bit Input Mode” on page 3–20
“Systolic FIR Mode” on page 3–21
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
3–9