DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 303

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Active Serial Configuration (Serial Configuration Devices)
Table 9–11. AS Timing Parameters for AS 1 and AS 4 Configurations in Stratix V Devices
May 2011 Altera Corporation
t
t
t
t
t
t
Notes to
(1) This information is preliminary.
(2) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
(3) t
(4) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on this pin, refer to
CO
SU
H
CD2UM
CD2CU
CD2UMC
Symbol
page
“Initialization” on page
CF2CD
Table
9–30.
, t
Estimating the Active Serial Configuration Time
Programming EPCS and EPCQ
CF2ST0
DCLK falling edge to AS_DATA0/ASDO output
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
9–11:
1
, t
CFG
, t
STATUS
Table 9–11
devices.
The AS configuration time is dominated by the time it takes to transfer data from the
EPCS to the Stratix V device. This serial interface is clocked by the Stratix V DCLK.
You can estimate the minimum AS ×1 mode configuration time by using the following
equation:
.rbf Size × (minimum DCLK period / 1 bit per DCLK cycle) = estimated minimum
configuration time.
You can estimate the minimum AS ×4 mode configuration time by using the following
equation:
.rbf Size × (minimum DCLK period / 4 bits per DCLK cycle) = estimated minimum
configuration time.
Enabling compression reduces the amount of configuration data that is transmitted to
the Stratix V device, which also reduces the configuration time. Your configuration
time is reduced based on the compression ratio. The compression ratio varies based
on the design.
EPCS and EPCQ are non-volatile, flash-memory-based devices. You can program
these devices in-system using a USB-Blaster™, EthernetBlaster, or ByteBlaster™ II
download cable. Alternatively, you can program EPCS or EPCQ device using a
microprocessor with the SRunner software driver.
If you are not using Quartus II software or SRunner software for EPCQ 256
programming, put your EPCQ 256 device into four-byte addressing mode before you
program and configure your device.
9–5.
, and t
CF2ST1
lists the timing parameters for AS 1 and AS 4 configurations in Stratix V
Parameter
timing parameters are identical to the timing parameters for PS mode listed in
(4)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
4 × maximum DCLK
t
CD2CU
CLKUSR period)
Minimum
period
+ (17,408 
175
1.5
—
0
(Note
Maximum
1), (2),
437
—
—
—
—
4
Table 9–12 on
(3)
Units
s
s
ns
ns
—
—
9–23