DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 379

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
PMA Architecture
May 2011 Altera Corporation
1
1
After the receiver power up and reset cycle, you must keep the CDR in LTR mode
until it locks to the input reference clock. When locked to the input reference clock, the
CDR output clock is trained to the configured data rate. The CDR now switches to
LTD mode to recover the clock from the incoming data. The LTR/LTD controller
controls the switch between the LTR and LTD modes.
Lock-to-Reference (LTR) Mode
In LTR mode, the phase frequency detector (PFD) in the CDR tracks the receiver input
reference clock. The PFD controls the charge pump that tunes the VCO in the CDR.
Depending on the data rate and the selected input reference clock frequency, the
Quartus II software automatically selects the appropriate /M and /L divider values
so the CDR output clock frequency is half the data rate. The pma_rx_is_lockedtoref
status signal is asserted active high to indicate that the CDR has locked to the phase
and frequency of the receiver input reference clock.
The phase detector is inactive in LTR mode and pma_rx_is_lockedtodata is ignored.
Lock-to-Data (LTD) Mode
During normal operation, the CDR must be in LTD mode to recover the clock from the
incoming serial data. In LTD mode, the phase detector in the CDR tracks the incoming
serial data at the receiver buffer. Depending on the phase difference between the
incoming data and the CDR output clock, the phase detector controls the CDR charge
pump that tunes the VCO.
The PFD is inactive in LTD mode. The pma_rx_is_lockedtoref signal toggles
randomly and has no significance in LTD mode.
After switching to LTD mode, the pma_rx_is_lockedtodata status signal is asserted. It
can take a maximum of 1 ms for the CDR to be locked to the incoming data and
produce a stable recovered clock. The actual lock time depends on the transition
density of the incoming data and the parts per million (PPM) difference between the
receiver input reference clock and the upstream transmitter reference clock. The
receiver PCS logic must be held in reset until the CDR produces a stable recovered
clock.
Automatic Lock Mode
In automatic lock mode, the LTR/LTD controller initially sets the CDR to lock to the
input reference clock (LTR mode). After the CDR locks to the input reference clock,
the LTR/LTD controller automatically sets it to lock to the incoming serial data
(LTD mode) when the following conditions are met:
■
■
■
Signal threshold detection circuitry indicates the presence of valid signal levels at
the receiver input buffer (PCI Express
defaults to true for all other configurations.)
The CDR output clock is within the configured PPM frequency threshold setting
with respect to the input reference clock (frequency locked)
The CDR output clock and the input reference clock are phase matched within
approximately 0.08 UI (phase locked)
®
[PCIe
®
Stratix V Device Handbook Volume 3: Transceivers
] configuration only. This condition
1–7