DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 471

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
PCI Express (PCIe)—Gen1 and Gen2
PCI Express (PCIe)—Gen1 and Gen2
May 2011 Altera Corporation
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The PCIe specification (version 2.0) provides implementation details for a
PCIe-compliant physical layer device at both Gen1 (2.5 Gbps) and Gen2 (5 Gbps)
signaling rates.
Stratix V devices have built-in PCIe hard IP blocks to implement the PHY MAC layer,
data link layer, and transaction layer of the PCIe protocol stack. The hard IP block
resides in the Embedded Hardcopy Block within the Stratix V device. To implement a
PCI Express-compliant PHY, configure the Stratix V transceiver in PCIe
configuration. If you enable the PCIe hard IP block, the transceiver interfaces with the
hard IP block. Otherwise, the transceiver interfaces directly with the FPGA fabric.
You can configure the Stratix V transceivers in a PCIe functional configuration using
one of the following methods:
■
■
For a description of the PCIe hard IP architecture and the allowed PCIe configurations
when you enable PCIe hard IP, refer to the
Stratix V devices support both Gen1 and Gen2 data rates in a PIPE configuration.
When configured for the Gen2 data rate, the Stratix V transceivers allow dynamic
switching between Gen2 and Gen1 line rates. Dynamic switching between the two
line rates is critical for speed negotiation during link training.
Stratix V transceivers support ×1, ×4, and ×8 lane configurations in both 2.5 Gbps and
5 Gbps data rates. In a PCIe ×1 configuration, the PCS and PMA blocks of each
channel are clocked and reset independently. PCIe ×4 and ×8 configurations support
channel bonding for four-lane and eight-lane PCIe links. In these bonded channel
configurations, the PCS and PMA blocks of all bonded channels share common clock
and reset signals.
PHY interface for PCI Express (PIPE)—PCIe hard IP block disabled
PCIe compiler—PCIe hard IP block enabled
PCI Express Compiler User
Stratix V Device Handbook Volume 3: Transceivers
Guide.
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