DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 160

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–20
Figure 4–16. PLL Locations for 5SGXB5 and 5SGXB6 Devices
Notes to
(1) Every index represents one fractional PLL in the device. The physical locations of the fractional PLLs correspond to the coordinates in the
(2) CLK0, CLK1, CLK20, and CLK21 clock pins feed into fractional PLL LR_X0_Y54 and fractional PLL LR_X0_Y63.
(3) CLK8, CLK9, CLK12, and CLK13 clock pins feed into fractional PLL LR_X197_Y54 and fractional PLL LR_X197_Y63.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Quartus II software Chip Planner.
Figure
4–16:
LR_X0_Y109
LR_X0_Y100
LR_X0_Y85
LR_X0_Y63
LR_X0_Y54
LR_X0_Y39
LR_X0_Y30
LR_X0_Y14
LR_X0_Y5
LR_X0_Y76
Figure 4–16
4
4
2
2
4
4
shows the PLL locations for 5SGXB5 and 5SGXB6 devices.
(2)
(2)
CLK[20..23][p,n]
CLK[0..3][p,n]
4 Logical clocks
4
Pins
Logical clocks
Pins
CEN_X90_Y123
CEN_X90_Y114
CEN_X90_Y11
CEN_X90_Y2
CLK[16..19][p,n]
CLK[4..7][p,n]
5SGXB5
5SGXB6
4
4 Logical clocks
Pins
(Note 1)
Pins
Logical clocks
CLK[12..15][p,n]
Chapter 4: Clock Networks and PLLs in Stratix V Devices
CLK[8..11][p,n]
4
4 Logical clocks
Pins
Logical clocks
Pins
(3)
(3)
4
2
2
4
4
4
LR_X197_Y109
LR_X197_Y100
LR_X197_Y85
LR_X197_Y76
LR_X197_Y63
LR_X197_Y54
LR_X197_Y39
LR_X197_Y30
LR_X197_Y14
LR_X197_Y5
May 2011 Altera Corporation
Stratix V PLLs