DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 7

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DK-DEV-5SGXEA7/ES

Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Datasheets

Specifications of DK-DEV-5SGXEA7/ES

Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
SV51001-1.8
Stratix V Family Variants
Stratix V Device Handbook
June 2011
June 2011
SV51001-1.8
f
This chapter provides an overview of the Stratix
of these devices and features are enabled in the Quartus
remaining devices and features will be enabled in future versions of the Quartus II
software.
To find out more about the upcoming Stratix V devices and features, refer to the
Stratix V Upcoming Device Features
Altera’s 28-nm Stratix V FPGAs include innovations such as an enhanced core
architecture, integrated transceivers up to 28 Gbps, and a unique array of integrated
hard intellectual property (IP) blocks. With these innovations, Stratix V FPGAs deliver
a new class of application-targeted devices optimized for:
Stratix V devices are available in four variants (GT, GX, GS, and E), each targeted for a
different set of applications. For higher volume production, you can prototype with
Stratix V FPGAs and use the low-risk, low-cost path to HardCopy
Stratix V GT devices, with both 28-Gbps and 12.5-Gbps transceivers, are optimized
for applications that require ultra-high bandwidth and performance in areas such as
40G/100G/400G optical communications systems and optical test systems.
Stratix V GX devices offer up to 66 integrated 14.1-Gbps transceivers supporting
backplanes and optical modules. These devices are optimized for high-performance,
high-bandwidth applications such as 40G/100G optical transport, packet processing,
and traffic management found in wireline, military communications, and network
test equipment markets.
Stratix V GS devices have an abundance of variable precision DSP blocks, supporting
up to 4,096 18×18 or 2,048 27×27 multipliers. In addition, Stratix V GS devices offer
integrated 14.1-Gbps transceivers, which support backplanes and optical modules.
These devices are optimized for transceiver-based DSP-centric applications found in
wireline, military, broadcast, and high-performance computing markets.
Stratix V E devices offer the highest logic density within the Stratix V family with
nearly one million logic elements (LEs) in the largest device. These devices are
optimized for applications such as ASIC and system emulation, diagnostic imaging,
and instrumentation.
Bandwidth-centric applications and protocols, including PCI Express
Gen3
Data-intensive applications for 40G/100G and beyond
High-performance, high-precision digital signal processing (DSP) applications
1. Stratix V Device Family Overview
document.
®
V devices and their features. Many
®
II software version 11.0. The
®
V ASICs.
®
(PCIe
Subscribe
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)

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