DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 308

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–28
Passive Serial Configuration
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
PS Configuration Using a MAX II Device or Microprocessor
f
You can perform PS configuration of Stratix V devices using an external host such as a
MAX II device, microprocessor, or a host PC. Therefore, the design that controls the
configuration stages, such as fetching the data from flash memory and sending it to
the device, must be stored in the external host.
The Parallel Flash Loader (PFL) feature in MAX II devices provide an efficient method
to program CFI flash memory devices through the JTAG interface. PFL also acts as a
controller to read configuration data from the flash memory device and configures the
Stratix V device. PFL supports both the PS and FPP configuration schemes.
For more information about the PFL, refer to the
User
The external host (a MAX II device or microprocessor) reads configuration data from
storage devices, such as flash memory, and transfers it to Stratix V devices. You can
store the configuration data in .pof, .rbf, .hex, or .ttf format. If you are using
configuration data in .rbf, .hex, or .ttf format, you must send the LSB of each data byte
first. For example, if the .rbf file contains the byte sequence 02 1B EE 01 FA, the serial
data transmitted to the device must be 0100-0000 1101-1000 0111-0111 1000-0000
0101-1111.
Figure 9–15
and a MAX II device for single device configuration.
Figure 9–15. Single Device PS Configuration Using an External Host
Notes to
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. V
(2) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device’s nCE pin.
(3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL, refer to
high enough to meet the V
up all the configuration system I/Os with V
Table 9–4 on page
Guide.
Figure
shows the configuration interface connections between a Stratix V device
9–15:
(MAX II Device or
Microprocessor)
External Host
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
ADDR
9–7.
Memory
IH
DATA0
specification of the I/O on the device and the external host. Altera recommends powering
CCPGM
V
10 k
CCPGM(1)
.
10 k
V
CCPGM(1)
GND
Parallel Flash Loader Megafunction
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix V Device
MSEL[4..0]
May 2011 Altera Corporation
Passive Serial Configuration
nCEO
N.C.
(3)
CCPGM
(2)
must be