DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 234

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

6–20
Figure 6–19. Receiver Datapath in Soft-CDR Mode
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
6–19:
f
10
Soft-CDR Mode
The Stratix V LVDS channel offers the soft-CDR mode to support the GbE and SGMII
protocols. A receiver PLL uses the local clock source for reference.
the soft-CDR mode datapath.
In soft-CDR mode, the synchronizer block is inactive. The DPA circuitry selects an
optimal DPA clock phase to sample the data. Use the selected DPA clock for bit-slip
operation and deserialization. The DPA block also forwards the selected DPA clock,
divided by the deserialization factor called rx_divfwdclk, to the FPGA fabric, along
with the deserialized data. This clock signal is put on the periphery clock (PCLK)
network. When using soft-CDR mode, the rx_reset port must not be asserted after
the rx_dpa_lock is asserted because the DPA will continuously choose new phase
taps from the PLL to track parts per million (PPM) differences between the reference
clock and incoming data.
For more information about PCLK networks, refer to the
Stratix V Devices
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
IOE
chapter.
2
Fractional PLL
3
DOUT DIN
Clock Mux
Bit Slip
(LVDS_LOAD_EN,
LVDS_diffioclk,
(Note
rx_outclk)
diffioclk
Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
1), (2),
rx_inclock
(3)
DOUT DIN
Synchronizer
8 Serial LVDS
Clock Phases
LVDS Receiver
3
Clock Networks and PLLs in
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
May 2011 Altera Corporation
Retimed
Data
DPA Clock
DPA Circuitry
Figure 6–19
DIN
Differential Receiver
+
LVDS Clock Domain
DPA Clock Domain
rx_in
shows