DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 277

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 8: Hot Socketing and Power-On Reset in Stratix V Devices
Power-On Reset Circuitry
Power-On Reset Circuitry
May 2011 Altera Corporation
1
1
Figure 8–1
Figure 8–1. Hot-Socketing Circuitry for Stratix V Devices
The POR circuit monitors the voltage level of the power supplies (V
V
device is in user mode. The weak pull-up resistor (R) in the Stratix V input/output
element (IOE) keeps the I/O pins from floating. The 3.0-V tolerance control circuit
permits 3.0 V to drive the I/O pins before the V
supplies are powered and prevents the I/O pins from driving out when the device is
not in user mode.
Altera uses GND as a reference for hot-socketing operations and I/O buffer designs.
To ensure proper operation, you must connect the GND between boards before
connecting the power supplies. This prevents the GND on your board from being
pulled up inadvertently by a path to power through other components on your board.
A pulled up GND could otherwise cause an out-of-specification I/O voltage or over
current condition with the Altera
For the V
connect all the VCCAUX pins.
This section describes POR circuitry in Stratix V devices. POR circuitry keeps the
devices in the reset state until the power supply outputs are within operating range.
When power is applied to a Stratix V device, a POR event occurs if the power supply
reaches the recommended operating range within the maximum power supply ramp
time (t
remain tri-stated, during which device configuration could fail. The maximum t
for Stratix V devices is 100 ms; the minimum t
selecting the MSEL pins. The standard or fast POR delay mode that is generated
internally from the MSEL decoding block determines the POR delay time, as follows:
CCPD
RAMP
, V
CCAUX
CCAUX
shows the I/O pin circuitry for Stratix V devices.
). If t
Resistor
Pull-Up
Weak
PAD
, V
power supply, POR only monitors one of the VCCAUX pins. You must
RAMP
CCBAT
R
is not met, the device I/O pins and programming registers
, and V
V
CCIO
CCPT
®
device.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
) and keeps the I/O pins tri-stated until the
Tolerance
to Logic Array
Voltage
Control
Input Buffer
RAMP
CC
, V
Output Enable
is 200 µs. Set the POR delay by
CCPT
, V
CCPD
Pre-Driver
Hot Socket
Output
Power On
Monitor
Reset
, and V
CC
, V
CCIO
CCPGM
power
RAMP
,
8–3