DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 476

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–20
Stratix V Device Handbook Volume 3: Transceivers
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In all PIPE configurations, (×1, ×4, and ×8), each receiver channel PCS has an optional
Electrical Idle Inference module designed to implement the electrical idle inference
conditions specified in the PCIe Base Specification 2.0.
Receiver Status
The PCIe specification requires the PHY to encode the receiver status on a 3-bit status
signal (pipe_rxstatus[2:0]). This status signal is used by the PHY-MAC layer for its
operation. The PIPE interface block receives status signals from the transceiver
channel PCS and PMA blocks, and encodes the status on the pipe_rxstatus[2:0]
signal to the FPGA fabric. The encoding of the status signals on the
pipe_rxstatus[2:0] signal is compliant with the PCIe specification.
signal, refer to the PCI Express PIPE PHY IP Core chapter in the
IP Core User
Receiver Detection
The PIPE interface block in Stratix V transceivers provides an input signal
(pipe_txdetectrx_loopback) for the receiver detect operation required by the PCIe
protocol during the detect substate of the LTSSM. When the
pipe_txdetectrx_loopback signal is asserted in the P1 power state, the PCIe interface
block sends a command signal to the transmitter buffer in that channel to initiate a
receiver detect sequence. In the P1 power state, the transmitter buffer must always be
in the electrical idle state. After receiving this command signal, the receiver detect
circuitry creates a step voltage at the output of the transmitter buffer. If an active
receiver (that complies with the PCIe input impedance requirements) is present at the
far end, the time constant of the step voltage on the trace is higher when compared
with the time constant of the step voltage when the receiver is not present. The
receiver detect circuitry monitors the time constant of the step signal seen on the trace
to determine if a receiver was detected. The receiver detect circuitry monitor requires
a 125-MHz clock for operation that you must drive on the fixedclk port.
For the receiver detect circuitry to function reliably, the AC-coupling capacitor on the
serial link and the receiver termination values used in your system must be compliant
with the PCIe Base Specification 2.0.
The PIPE core provides a 1-bit PHY status (pipe_phystatus) and a 3-bit receiver
status signal (pipe_rxstatus[2:0]) to indicate whether a receiver was detected or not,
as per the PIPE 2.0 specifications.
For more information about input signals and status signals related to receiver
detection, refer to the PCI Express PIPE PHY IP Core chapter in the
PHY IP Core User
Clock Rate Compensation Up to ±300 PPM
In compliance with the PCIe protocol, Stratix V receiver channels are equipped with a
rate match FIFO to compensate for small clock frequency differences up to ±300 PPM
between the upstream transmitter and the local receiver clocks.
For information about the encoding of status signals on the pipe_rxstatus[2:0]
Guide.
Guide.
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
PCI Express (PCIe)—Gen1 and Gen2
Altera Transceiver PHY
May 2011 Altera Corporation
Altera Transceiver