DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 85

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices
Adaptive Logic Modules
May 2011 Altera Corporation
ALM Operating Modes
One ALM contains four programmable registers. Each register has data, clock, clock
enable, synchronous and asynchronous clear, and synchronous load and clear inputs.
Global signals, general-purpose I/O pins, or any internal logic can drive the register’s
clock and clear-control signals. Either general-purpose I/O pins or internal logic can
drive the clock enable. For combinational functions, the register is bypassed and the
output of the LUT drives directly to the outputs of an ALM.
Each ALM has two sets of outputs that drive the local, row, and column routing
resources. The LUT, adder, or register outputs can drive these output drivers (refer to
Figure
or direct-link routing connections. One of these ALM outputs can also drive local
interconnect resources. This allows the LUT or adder to drive one output while the
register drives another output.
This feature, called register packing, improves device utilization because the device
can use the register and the combinational logic for unrelated functions. Another
special packing mode allows the register output to feed back into the LUT of the same
ALM so that the register is packed with its own fan-out LUT. This provides another
mechanism for improved fitting. The ALM can also drive out registered and
unregistered versions of the LUT or adder output.
The Stratix V ALM operates in one of the following modes:
■
■
■
■
Each mode uses ALM resources differently. In each mode, eleven available inputs to
an ALM—the eight data inputs from the LAB local interconnect, carry-in from the
previous ALM or LAB, the shared arithmetic chain connection from the previous
ALM or LAB, and the register chain connection—are directed to different destinations
to implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, synchronous clear, synchronous load, and clock enable control for
the register. These LAB-wide signals are available in all ALM modes.
For more information about the LAB-wide control signals, refer to
Signals” on page
The Quartus II software and supported third-party synthesis tools, in conjunction
with parameterized functions such as the library of parameterized modules (LPM)
functions, automatically choose the appropriate mode for common functions such as
counters, adders, subtractors, and arithmetic functions.
Normal Mode
Normal mode is suitable for general logic applications and combinational functions.
In this mode, up to eight data inputs from the LAB local interconnect are inputs to the
combinational logic. Normal mode allows two functions to be implemented in one
Stratix V ALM, or a single function of up to six inputs. The ALM can support certain
combinations of completely independent functions and various combinations of
functions that have common inputs.
“Normal Mode” on page 1–7
“Extended LUT Mode” on page 1–9
“Arithmetic Mode” on page 1–10
“Shared Arithmetic Mode” on page 1–11
1–6). For each set of output drivers, two ALM outputs can drive column, row,
1–3.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
“LAB Control
1–7