DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 460

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–4
Figure 4–3. Channel Datapath in a 10GBASE-R Configuration
Stratix V Device Handbook Volume 3: Transceivers
tx_coreclk
tx_clkout
rx_coreclk
rx_clkout
Fabric
FPGA
8-Bit Control
8-Bit Control
64-Bit Data
64-Bit Data
Supported Features
f
CMU PLL
(From the ×1 Clock Lines)
Figure 4–3
The following sections describe the features supported by Stratix V transceivers in a
10GBASE-R configuration.
For details about 10GBASE-R PHY IP control and status signals associated with each
feature, refer to the 10GBASE-R PHY IP Core chapter in the
Core User
64-Bit Single Data Rate (SDR) Interface to the MAC/RS
Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between
the 10GBASE-R PCS and the Ethernet MAC/RS. The XGMII interface defines 32-bit
data and 4-bit wide control character clocked between the MAC/RS and the PCS at
both the positive and negative edge (DDR) of the 156.25 MHz interface clock.
Serial Clock
8-Bit Control
64-Bit Data
Guide.
shows the transceiver datapath in a 10GBASE-R configurations.
Central/ Local Clock Divider
BER
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
8-Bit Control
64-Bit Data
66
66
Clock Divider
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
Parallel and Serial Clocks
(Only from the Central Clock Divider)
66
Transmitter 10G PCS
Receiver 10G PCS
66
Altera Transceiver PHY IP
40
May 2011 Altera Corporation
40
Parallel Clock
Serial Clock
Parallel and Serial Clock
Transmitter PMA
Receiver PMA
10GBASE-R