DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 421

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Transceiver Clocking in Stratix V Devices
Internal Clocking
May 2011 Altera Corporation
Transmitter Clock Network
1
Figure 2–5. Internal Clocking
The reference clock from one of the sources shown in
a transmit PLL. The transmit PLL could be either a CMU PLL or an ATX PLL. The
transmit PLL generates a serial clock that is distributed using a transmitter clock
network to the transceiver channels.
Clocking described in this section is internal to the transceiver, and clock routing is
primarily performed by the Quartus II software based on the transceiver
configuration selected.
The transmitter clock network routes the clock from the transmit PLL to the
transmitter channel (as shown in
transmitter channel:
■
■
Stratix V transceivers support various non-bonded and bonded transceiver clocking
configurations. If you use a bonded configuration, both the serial clock and parallel
clock are routed from the transmit PLL to the transmitter channel. If you use a
non-bonded configuration, then only the serial clock is routed from the transmit PLL
to the transmitter channel and the parallel clock is generated by the local clock divider
or central clock divider of each channel.
Serial clock—high-speed clock for the serializer
Parallel clock—low-speed clock for the serializer and the PCS
×1
Clock Lines
×6
Transmit
PLL
×N
Transmitter
Network
Clock
A
Figure
2–5) and provides two clocks to the
Transceiver Channel
Transceiver Channel
Transmitter
Transmitter
Receiver
Receiver
Stratix V Device Handbook Volume 3: Transceivers
C
B
Figure 2–2 on page 2–2
Reference Clock
Reference Clock
Input
Input
CDR
CDR
tx_serial_data
rx_serial_data
tx_serial_data
rx_serial_data
is fed to
2–5